Offset compensation for sense amplifiers

ABSTRACT

A sense amplifier includes a first transistor having a first gate, a second transistor having a second gate in series with the first transistor, a third transistor having a third gate, and a fourth transistor having a fourth gate in series with the third transistor. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first and second transistors or the third and fourth transistors, the first compensation transistor having a first compensation bulk. The first compensation bulk receives a first compensation voltage to modify the first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first and second input nodes.

PRIORITY CLAIM

The present application is a continuation of U.S. application Ser. No. 13/728,637, filed Dec. 27, 2012, which is a divisional of U.S. application Ser. No. 12/903,652, filed on Oct. 13, 2010, now U.S. Pat. No. 8,362,807, issued Jan. 29, 2013, which are incorporated by reference herein in their entireties.

TECHNICAL FIELD

The present disclosure is generally related to sense amplifiers, and, more particularly, to offset compensation for sense amplifiers.

BACKGROUND

A sense amplifier (SA) is used to sense the difference between two signals at two inputs of the sense amplifier, and amplify the difference or, commonly stated, amplify the differential signal across the inputs. To sense correctly, a sense margin, which is the minimum difference between the two signals, or the minimum differential signal, is required.

In many situations, process variation causes two different threshold voltages to be present in two transistors that are supposed to be the same (e.g., two NMOS transistors of a cross latch of an amplifier). In that situation, the sense amplifier is said to have an offset at the two inputs caused by the mismatch of the two transistors. As a result, the sense amplifier favors reading one logic state versus another logic state, instead of neutrally providing the sensed data. For example, some sense amplifiers, when sensing the differential signal across two inputs, tend to favor a high logic level, (e.g., a High) while some other sense amplifiers tend to favor a low logic level (e.g., a Low). A sense amplifier tending to favor a High quickly provides the High as the read data at the output when the actual High data is sensed, but slowly provides a Low as the read data at the output when the actual Low data is sensed. Similarly, a sense amplifier tending to favor a Low quickly provides the Low when the actual Low data is sensed, but slowly provides a High when the actual High data is sensed.

In effect, because of the process variation, the mismatch manifests as an additional offset, which causes the sense amplifier to require a larger sense margin to correctly sense the data. In applications where one sense margin is used for many amplifiers, a larger value for the sense margin is utilized so that a very high percentage, or all, of the sense amplifiers function correctly. As the large sense margin is used, the time required for the differential signal to develop increases, making the overall memory access speed slower.

BRIEF DESCRIPTION OF THE DRAWINGS

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the detailed description below. Other features and advantages will be apparent from the detailed description, drawings, and claims.

FIG. 1 is a diagram of a sense amplifier having compensation circuitry, in accordance with some embodiments.

FIG. 2 is a diagram of a circuit illustrating a first mechanism to compensate for the offset of the sense amplifier in FIG. 1, in accordance with some embodiments.

FIG. 3 is a diagram of a circuit illustrating a second mechanism to compensate for the offset of the sense amplifier in FIG. 1, in accordance with some embodiments.

FIG. 4 is a flow chart illustrating a method of compensating the offset for a plurality of the sense amplifiers used in a memory, in accordance with some embodiments.

FIG. 5 is a diagram of a sense amplifier having compensation circuitry, in accordance with some further embodiments.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Embodiments, or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art. Reference numbers may be repeated throughout the embodiments, but they do not require that feature(s) of one embodiment apply to another embodiment, even if they share the same reference number.

Some embodiments can have one or a combination of the following features and/or advantages. The re-offset voltage provided to the bulks of the compensation transistors reduces the sense margin. As a result, the memory access time is improved.

Exemplary Sense Amplifiers with Compensation Mechanisms

FIG. 1 is a diagram of a sense amplifier (SA) 100, in accordance with some embodiments. In some embodiments, sense amplifier 100 is used in memory arrays, but SA 100 can be used in other circuits where a small signal difference is to be amplified, including, for example, an IO interface. In some memory applications, multiple memory cells on a column share the same amplifier.

SA 100 senses a high logic level (e.g., a High) at output Out when the voltage value at input SAIN_H is greater than the voltage value at input SAIN_L. Similarly, SA 100 senses a low logic level (e.g., a Low) at output Out when the voltage value at input SAIN_H is lower than the voltage value at input SAIN_L. Transistor N3 operates as a switch and serves as a current path for SA to be turned on/off. For example, when signal SAE is applied with a High, transistor N3 turns on, and provides a current path for SA 100 to turn on. In contrast, when signal SA is applied with a Low, transistor N3 turns off, and SA 100 turns off because there is no current path.

In some embodiments, for various reasons, including device manufacturing process variations, transistor N1 and transistor N2 are not exactly the same (i.e., mismatched). As a result, transistor N1 has a threshold voltage (e.g., threshold voltage Vthn1) different from that of transistor N2 (e.g., threshold voltage Vthn2), which causes an offset at inputs SAIN_H and SAIN_L. Because of the mismatch in the transistors, or the offset, at inputs SAIN_H and SAIN_L, sense amplifier 100 favors reading a logic state versus another logic state, instead of neutrally providing the sensed data. For example, if voltage Vthn1 is greater than voltage Vthn2, then SA 100 favors reading a Low on node SAIN_H when node SAIN_H serves as an output. If voltage Vthn1 is less than voltage Vthn2, then SA 100 favors reading a High on node SAIN_H when node SAIN_H serves as an output. For illustration, voltage ΔVth represents the difference between threshold voltage Vthn1 and threshold voltage Vthn2. Voltage ΔVth is positive if voltage Vthn1 is greater than voltage Vthn2, and voltage ΔVth is negative if voltage Vthn1 is less than voltage Vthn2. Further, voltage ΔInput represents the offset at inputs SAIN_H and SAIN_L corresponding to voltage ΔVth. In some embodiments, mechanisms are provided to compensate (e.g., reduce, cancel, re-offset, etc.) the effect of the threshold voltage offset (e.g., the voltage difference) ΔVth, and after the threshold offset ΔVth is re-offset, the input voltage offset caused by the threshold offset is reduced or canceled (e.g., re-offset). For simplicity of illustration, reducing or re-offsetting the offset described in this document could cancel the offset altogether.

PMOS transistors PO1 and PO2 are commonly called compensation transistors, and serve to re-offset (e.g., cancel, reduce, compensate, etc.) the offset caused by the mismatch between transistors N1 and N2. When compensation is desired, one or a combination of the bulk of transistor PO1 and PO2 is provided with one or a combination of bulk re-offset voltages (e.g., Vrob, Vrob1, Vrob2 illustrated below) that compensates for the mismatch. Alternatively stated, the bulk re-offset voltage(s) cancels the input offset at the corresponding input SAIN_H and/or SAIN_L. In some embodiments, the gates of transistors PO1 and PO2 are coupled together and to ground (e.g., Low) so that transistors PO1 and PO2 are turned on for re-offsetting. In the following explanation, for ease of discussion, when one re-offset voltage is provided to the bulk of one PMOS transistor (e.g., transistor PO2), the bulk of the other PMOS transistor (e.g., transistor PO1) remains the same (e.g., at voltage Vdd).

In some embodiments, if voltage Vthn1 is greater than voltage Vthn2 (e.g., voltage ΔVth is positive, and sense amplifier 100 favors reading a Low), a negative bulk re-offset voltage Vrob is provided to the bulk of transistor PO2, which cancels the offset at inputs SAIN_L and SAIN_H that corresponds to the threshold voltage difference ΔVth. But if voltage Vthn1 is less than voltage Vthn2 (e.g., voltage ΔVth is negative, and sense amplifier 100 favors reading a Low), a negative bulk re-offset voltage Vrob is provided to the bulk of transistor PO1, which also cancels the offset at inputs SAIN_L and SAIN_H corresponding to the threshold voltage difference ΔVth. Once voltage Vrob is provided to the bulk of transistor PO2 or transistor PO1, the threshold voltage of the corresponding transistor (e.g., voltage Vthp2 or voltage Vthp1) changes, which re-offsets the offset caused by the mismatch (e.g., the difference in the threshold voltages) between transistors N1 and N2.

In some embodiments, the mismatch between transistors N1 and N2 causing the offset exists after sense amplifier 100 is manufactured, and the difference in the threshold voltage ΔVth is identified by a Monte Carlo simulation. Based on the identified ΔVth, the re-offset voltage Vrob is determined and provided to the bulk of the corresponding transistor PO1 or PO2.

In some embodiments, a plurality of sense amplifiers (e.g., sense amplifiers 100) is used in a circuit (e.g., in a memory array), and the minimum sense margin (e.g., Smin) for the plurality of sense amplifiers is known. For example, the minimum sense margin Smin is the mean of the sense margins of all sense amplifiers plus three sigma. The sense amplifiers are then configured to sense some known data based on the known (i.e., pre-determined) sense margin. In some embodiments related to a memory array, a built-in self test (BIST) is used to test the sense amplifiers used in the memory array. For example, for each sense amplifier the minimum read margin is set for the sense amplifier, the BIST is invoked for the sense amplifier to test itself using a specific input data (e.g., a Low or a High). The test result is compared against the expected test data from which the sense amplifiers are classified into a group of sense amplifiers favoring reading a High (e.g., group I) and/or another group of sense amplifiers favoring reading a Low (e.g., group II).

For example, sense amplifiers that are supposed to provide a Low after sensing, but provide the failed data, reveal that the sense amplifiers favor reading a High and thus are classified into group I. Similarly, sense amplifiers that are supposed to provide a High after sensing but failed the sensing reveal that those amplifiers favor reading a Low and are classified into group II. For each sense amplifier in group I, a corresponding positive bulk re-offset voltage Vrob is provided to the bulk of transistor PO2, which, in effect, provides the input re-offset to input SAIN_L. At the same time, the bulk of each transistor PO2 in group I remains unchanged, e.g., at voltage Vdd. Similarly, for each sense amplifier in group II, a corresponding bulk re-offset voltage Vrob is provided to the bulk of transistor PO1, which, in effect, provides the input re-offset to input SAIN_H. At the same time, the bulk of each transistor PO1 in group II remains unchanged, e.g., at voltage Vdd.

In some embodiments, re-offset voltage Vrob is calculated based on the difference in the threshold voltage of transistor N1 (e.g., Vthn1) and that of transistor N2 (e.g., Vthn2), e.g., voltage ΔVt. If voltage ΔVt is 0, then the offset is 0, and re-offset voltage Vrob is 0 V. But if voltage ΔVt is not 0, voltage ΔVt is used to generate the difference in threshold voltages of transistors PO1 and PO2 (e.g., ΔVtp) to re-offset the voltage difference ΔVt of transistors N1 and N2, by, for example, changing one or a combination of the threshold voltage of transistors PO1 and PO2. For example, if ΔVt is 100 mV, then the threshold voltage of transistor PO1 (e.g., voltage Vthpo1) is configured to change by 100 mV, while the threshold voltage of transistor PO2 (e.g., voltage Vthpo2) remains unchanged, or voltage Vthpo2 of transistor PO2 is configured to change by −100 mV while voltage Vthpo1 of transistor PO1 remains unchanged. Alternatively, voltage Vthpo1 is configured to change by 40 mV, 50 mV, or 60 mV, and voltage Vthpo2 is configured to change by −60 mV, −50 mV, and −40 mV, etc., respectively. For illustration, the threshold voltage of transistors PO2 is adjusted. In other words, threshold voltage Vthpo2 is changed by −ΔVtp where ΔVtp=ΔVt. In some embodiments, ΔVtp is generated by providing negative voltage Vrob to the bulk of transistor PO2. Further, voltage Vrob is calculated based on the equation:

V _(TN) =V _(TO)+γ(√{square root over (V _(SB)+2φ_(F))}−√{square root over (2φ_(F))})

where V_(TN) is the threshold voltage of transistor PO2 when the substrate bias is present, V_(SB) is the source-to-body substrate bias (e.g., Vrob), 2φ_(F) is the surface potential, and V_(TO) is the threshold voltage for zero substrate bias and y is the body effect parameter.

FIG. 1 is illustrated with the transistor PO1 coupled between transistors P1 and N1, and transistor PO2 coupled between transistors P2 and N2. Various embodiments are not so limited. Transistor PO1 can be coupled between voltage Vdd and transistor P1 while transistor PO2 can be coupled between voltage Vdd and transistor P2. The sign of re-offset voltage Vrob, however, is changed accordingly, as recognizable by persons of ordinary skilled in the art. For example, when voltage Vthn1 is greater than voltage Vthn2 (e.g., voltage ΔVth is positive), a corresponding positive re-offset voltage Vrob is applied at the bulk of transistor PO2, and when voltage Vthn2 is less than voltage Vthn2 (e.g., voltage ΔVth is negative), a corresponding positive re-offset voltage Vrob is applied at the bulk of transistor PO1, etc.

Exemplary Offset Circuits

FIG. 2 is a diagram of a circuit 200 illustrating offset compensation for SA 100, in accordance with some embodiments. In this illustration, the bulk of one transistor (e.g., transistor PO1 or PO2) remains the same (e.g., at voltage Vdd) while the bulk of the other transistor is provided with bulk re-offset voltage Vrob. In some embodiments, the bulk of PMOS transistors without a re-offset is set at voltage Vdd, and the bulk of the transistor receiving the offset is provided with voltage Vdd+Vrob to provide the re-offset voltage Vrob. For example, if the re-offset is for transistor PO2, then the bulk of transistor PO2 is provided with Vdd+Vrob, while the bulk of transistor PO1 remains the same at voltage Vdd. Similarly, if the re-offset is to transistor PO1, then the bulk of transistor PO1 is provided with Vdd+Vrob, while the bulk of transistor PO2 remains the same at voltage Vdd. In some embodiments, re-offsetting to the bulk of transistor PO2 with a re-offset voltage value Vrob results in a re-offset at input SAIN_L with a corresponding voltage value Vroi. Similarly, re-offsetting to the bulk of transistor PO1 with a re-offset voltage value results in a re-offset at input SAIN_H with a corresponding voltage value Vroi.

In FIG. 2, when signal SET is activated (e.g., applied with a High), NMOS transistor N21 turns on, which pulls node NO21, which is the drain of transistor N21, to ground (e.g., Low). As a result, transistor PPG1 is turned on, and voltage Vdd+Vrob is passed through transistor PPG1 to the bulk of transistor PO2. In effect, the bulk of transistor PO2 is provided with a re-offset voltage value of Vrob. Node NO21 pulled low also causes transistor P22 to turn on, which transfers voltage Vdd at the source of transistor P22 to the drain of transistor P22 or to the bulk of transistor PO1.

Similarly, when signal RESET is activated (e.g., applied with a High), NMOS transistor N22 turns on, which pulls node NO22, which is the drain of transistor N22, to ground (e.g., Low). As a result, transistor PPG2 is turned on, and voltage Vdd+Vrob is passed through transistor PPG2 to the bulk of transistor PO1. In effect, the bulk of transistor PO1 is provided with a re-offset voltage value of Vrob. Node NO22 being Low also causes transistor P21 to turn on, which transfers voltage Vdd at the source of transistor P21 to the drain of transistor P21 or to the bulk of transistor PO2.

Latch Ltch stores the value passed through transistors PPG1 and PPG2 at nodes NO21 and NO22, respectively.

In the above illustration, the bulk of one transistor (e.g., transistor PO1 or PO2) is re-offset and the bulk of the other transistor remains the same. In some embodiments, the bulks of both transistors PO1 and PO2 are re-offset. FIG. 3 is a diagram of a circuit 300 illustrating re-offsetting to the bulk of both transistors PO1 and PO2. In this illustration, the bulk of transistor PO1 is re-offset with a first value, e.g., voltage Vrob1, by a sub-circuit 300A, and the bulk of transistor PO2 is re-offset with a second value, e.g., voltage Vrob2, by a sub-circuit 300B. Circuits 300A and 300B include similar components and operate in the same manner except circuit 300A is used to re-offset the bulk of transistor PO1 while circuit 300B is used to re-offset the bulk of transistor PO2. Further, a circuit 300A or 300B operates substantially the same as circuit 200. For simplicity, only one circuit, e.g., circuit 300A is described, and the operation of the other circuit, e.g., circuit 300B, can be understood by a person of ordinary skill in the art. When there is no compensation or re-offset, signal SET1 is activated, transistor PPG1 is turned on and voltage Vdd is passed to the bulk of transistor PO1. But when a re-offset value, e.g., voltage Vrob1 is desired, signal RESET1 is activated, transistor PPG2 is activated, and voltage Vdd+Vrob1 is passed to the bulk of transistor PO1. In effect, the bulk of transistor PO1 is re-offset with voltage Vrob1.

In circuit 300, voltage Vrob1 or voltage Vrob2 is negative or positive, and the total re-offset by voltage Vrob1 to the bulk of transistor PO1 and voltage Vrob2 to the bulk of transistor PO2 is to reduce the effect of the mismatch between transistor N1 and N2.

Exemplary Method of Re-Offsetting a Plurality of Sense Amplifiers

FIG. 4 is a flowchart illustrating a method 400 of re-offsetting a plurality of sense amplifiers used in a memory array, in accordance with some embodiments. Method 400, however, can be used for sense amplifiers in other circuits.

In step 405, re-offset voltage Vrob is set to 0 V.

In step 408, re-offset voltage Vrob is applied to all sense amplifiers.

In step 410, a BIST is invoked for the sense amplifiers to sense and verify the sense results of the sense amplifiers.

In step 415, if all sense amplifiers pass, the applied voltage Vrob is identified as the desired re-offset voltage in step 417. If, however, any of the amplifiers fails, the failed amplifiers are grouped into a first group favoring reading a High (e.g., group I) and/or a second group favoring reading a Low (e.g., group II) in step 418.

In step 420, re-offset voltage Vrob is changed (e.g., is decreased, for example, by −100 mV, in some embodiments), and the new re-offset voltage (e.g., voltage Vrobn) is applied in step 410, in accordance with the identified groups. For example, for amplifiers in group I, voltage Vrobn is applied to the bulk of transistor PO1 while, for amplifiers in group II, voltage Vrobn is applied to the bulk of transistors PO2. When all amplifiers pass (e.g., in step 415), a first re-offset voltage (e.g., voltage Vrob1) is identified for group I, and a second re-offset voltage (e.g., voltage VrobII) is identified for group II, in step 417.

In flow chart 400, a sequential search (e.g., voltage Vrobn keeps decreasing) is used for illustration. However, other searches, including a binary search are within the scope of various embodiments.

Exemplary Sense Amplifier with Compensation Mechanisms—Some Further Embodiments

FIG. 5 is a diagram of a sense amplifier (SA) 500 having offset compensation circuitry, in accordance with some further embodiments. Compared with SA 100, SA 500 includes two NMOS transistors NO1 and NO2 that replace PMOS transistors PO1 and PO2, respectively. The gates of transistors NO1 and NO2, however, are coupled to voltage Vdd (e.g., a High) plus Vthn, the threshold voltage of transistors NO1 and NO2, so that transistors NO1 and NO2 are turned on for re-offsetting. Further, the drains of transistors NO1 and NO2 are coupled to the drains of transistors P1 and P2, respectively, and the source of transistors NO1 and NO2 are coupled to the drains of transistor N1 and N2, respectively.

The re-offset operation of transistors NO1 and NO2 is substantially the same as that of transistors PO1 and PO2. For example, when voltage Vthn1 is greater than voltage Vthn2 (e.g., voltage ΔVth is positive), a corresponding positive re-offset voltage Vrob is applied at the bulk of transistor NO2, and when voltage Vthn1 is less than voltage Vthn2 (e.g., voltage ΔVth is negative), a corresponding positive re-offset voltage Vrob is applied at the bulk of transistor NO1, etc. Different techniques (e.g., having one or two re-offset voltages, negative and/or positive re-offset voltages, etc.) applicable to SA 100 are applicable to SA 500 as would be recognizable by a person of ordinary skill in the art.

FIG. 5 is illustrated with the transistor NO1 coupled between transistors P1 and N1, and transistor NO2 coupled between transistors P2 and N2. Various embodiments are not so limited. Transistor NO1 can be coupled between transistor N1 and transistor N3 while transistor NO2 can be coupled between transistor N2 and transistor N3. The sign of re-offset voltage Vrob, however, is changed accordingly, as recognizable by persons of ordinary skilled in the art. For example, when voltage Vthn1 is greater than voltage Vthn2 (e.g., voltage ΔVth is positive), a corresponding negative re-offset voltage Vrob is applied at the bulk of transistor NO2, and when voltage Vthn1 is less than voltage Vthn2 (e.g., voltage ΔVth is negative), a corresponding negative re-offset voltage Vrob is applied at the bulk of transistor NO1, etc.

In the above illustration (e.g., FIG. 1 and FIG. 5), one pair of transistors (e.g., the pair of transistor PO1 and PO2 or the pair of transistor NO1 and NO2) is used. Combinations of pairs of transistors are within the scope of various embodiments, and are recognizable by persons of ordinary skill in the art. For example, a pair of NMOS transistors NO1 and NO2 can be added to circuit 100 by having transistor NO1 coupled between transistor PO1 and transistor N1 or between transistor N1 and transistor N3, and transistor NO2 coupled between transistor PO2 and transistor N2 or between transistor N2 and transistor N3. Similarly, a pair of PMOS transistors PO1 and PO2 can be added to circuit 500 by having transistor PO1 coupled between transistor P1 and voltage Vdd node and transistor PO2 coupled between transistor P2 and voltage Vdd node, etc.

A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, the various transistors being shown as a particular dopant type (e.g., NMOS and PMOS) are for illustration purposes, embodiments of the disclosure are not limited to a particular type, but the dopant type selected for a particular transistor is a design choice and is within the scope of various embodiments. The logic level (e.g., low or high) of the various signals used in the above description is also for illustration purposes, various embodiments are not limited to a particular level when a signal is activated and/or deactivated, but, rather, selecting such a level is a matter of design choice. In some embodiments, a source/drain is used for either a source or a drain of a transistor.

Some embodiments are described as having one bulk voltage re-offset applied at a bulk of one transistor PO1 or PO2, and some embodiments are described as having two bulk re-offset voltages applied at the bulks of both transistors PO1 and PO2. Various embodiments of the invention are not limited to a particular mechanism of re-offsetting by using one or two bulk re-offset voltages. Selecting one or two re-offset voltages is a design choice and is within the scope of the various embodiments. In various embodiments, when a re-offset is applied, the re-offset value is either positive or negative and can be applied to a corresponding transistor. For example, in the above illustration, when voltage Vthn1 is greater than voltage Vthn2, a negative re-offset voltage Vrob is applied to the bulk of transistor PO2. Alternatively, a positive re-offset of the same value can be applied to the bulk of transistor PO1. Various embodiments are not limited to a positive or a negative value, nor applying to one particular transistor. For example, when a bulk re-offset voltage corresponding to voltage ΔVth is identified, the re-offset voltage can be applied to a particular transistor, or the same negative offset can be applied to the other transistor, or the bulk re-offset can be split into two and applied to both transistors. For example, the bulk re-offset is Vrob identified, from which ½ Vrob can be applied to the bulk of a transistor (e.g., transistor PO1) and −½ Vrob can be applied to the bulk of the other transistor (e.g., transistor PO2), etc.

In some embodiments, a sense amplifier comprises a first transistor having a first gate, a second transistor in series with the first transistor, the second transistor having a second gate, a third transistor having a third gate, and a fourth transistor in series with the third transistor, the fourth transistor having a fourth gate. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first transistor and the second transistor or the third transistor and the fourth transistor, the first compensation transistor having a first compensation threshold and a first compensation bulk. The sense amplifier is configured to have the first compensation bulk receive a first compensation voltage to modify the first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first input node and the second input nodes.

In some embodiments, a sense amplifier circuit comprises a sense amplifier, the sense amplifier comprising a first transistor having a first gate, a second transistor in series with the first transistor, the second transistor having a second gate, a third transistor having a third gate, and a fourth transistor in series with the third transistor, the fourth transistor having a fourth gate. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first transistor and the second transistor or the third transistor and the fourth transistor, the first compensation transistor having a first compensation bulk. An offset circuit is configured to supply a first compensation voltage to the first compensation bulk to modify a first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first input node and the second input node.

In some embodiments, a sense amplifier circuit comprises a first power node having a first voltage value, a second power node having a second voltage value different from the first voltage value, and a sense amplifier. The sense amplifier comprises a first branch between the first power node and the second power node, the first branch comprising a first complementary transistor pair and a first input node between the transistors of the first complementary transistor pair, a second branch between the first power node and the second power node, the second branch comprising a second complementary transistor pair and a second input node between the transistors of the second complementary transistor pair, and a compensation transistor in the first branch or the second branch. The first input node is coupled to a gate of each transistor of the second complementary transistor pair and the second input node is coupled to a gate of each transistor of the first complementary transistor pair. An offset circuit is configured to supply a compensation voltage to a bulk of the compensation transistor, the compensation voltage being selectable between the first voltage value and a compensation voltage value equal to the first voltage value increased or decreased by a re-offset voltage value.

The above methods show exemplary steps, but they are not necessarily performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments. 

What is claimed is:
 1. A sense amplifier comprising: a first transistor having a first gate; a second transistor in series with the first transistor, the second transistor having a second gate; a third transistor having a third gate; a fourth transistor in series with the third transistor, the fourth transistor having a fourth gate; a first input node coupled to the third gate and the fourth gate; a second input node coupled to the first gate and the second gate; and a first compensation transistor in series with the first transistor and the second transistor or the third transistor and the fourth transistor, the first compensation transistor having a first compensation bulk, wherein the sense amplifier is configured to have the first compensation bulk receive a first compensation voltage to modify a first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first input node and the second input node.
 2. The sense amplifier of claim 1, wherein the first compensation transistor is in series with the first transistor and the second transistor, and the sense amplifier circuit further comprises a second compensation transistor in series with the third transistor and the fourth transistor, the second compensation transistor having a second compensation bulk.
 3. The sense amplifier of claim 2, wherein the sense amplifier circuit is configured to have the second compensation bulk receive a second compensation voltage different from the first compensation voltage.
 4. The sense amplifier of claim 1, wherein the value calculated to compensate for the offset is based on an equation: V _(TN) =V _(TO)+γ(√{square root over (V _(SB)+2φ_(F))}−√{square root over (2φ_(F))}) where V_(TN) is the first compensation threshold, V_(TO) is a threshold voltage of the first compensation transistor for zero substrate bias, γ is a body effect parameter, 2_(φF) is a surface potential, and V_(SB) is a difference between zero substrate bias and the value calculated to compensate for the offset.
 5. The sense amplifier of claim 1, wherein the first compensation transistor is a PMOS transistor.
 6. The sense amplifier of claim 1, wherein the first compensation transistor is an NMOS transistor.
 7. A sense amplifier circuit comprising: a sense amplifier, the sense amplifier comprising: a first transistor having a first gate; a second transistor in series with the first transistor, the second transistor having a second gate; a third transistor having a third gate; a fourth transistor in series with the third transistor, the fourth transistor having a fourth gate; a first input node coupled to the third gate and the fourth gate; a second input node coupled to the first gate and the second gate; and a first compensation transistor in series with the first transistor and the second transistor or the third transistor and the fourth transistor, the first compensation transistor having a first compensation bulk; and an offset circuit configured to supply a first compensation voltage to the first compensation bulk to modify a first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first input node and the second input node.
 8. The sense amplifier circuit of claim 7, wherein the offset circuit comprises a pair of latched transistors, the first transistor of the pair of latched transistors is configured to pass the calculated value to the bulk of the first compensation transistor, and the second transistor of the pair of latched transistors is configured to pass a voltage value different from the calculated value to the bulk of the first compensation transistor.
 9. The sense amplifier circuit of claim 8, wherein the offset circuit is configured to select between the calculated value and the different voltage value in response to a pair of activation signals.
 10. The sense amplifier circuit of claim 7, wherein the first compensation transistor is in series with the first transistor and the second transistor, and the sense amplifier further comprises a second compensation transistor in series with the third transistor and the fourth transistor, the second compensation transistor having a second compensation bulk.
 11. The sense amplifier circuit of claim 10, wherein the offset circuit is configured to supply a second compensation voltage to the second compensation bulk, the second compensation voltage being different from the first compensation voltage.
 12. The sense amplifier circuit of claim 10, further comprising a second offset circuit configured to supply a second compensation voltage to the second compensation bulk.
 13. The sense amplifier circuit of claim 7, wherein the value calculated to compensate for the offset is based on an equation: V _(TN) =V _(TO)+γ(√{square root over (V _(SB)+2φ_(F))}−√{square root over (2φ_(F))}) where V_(TN) is the first compensation threshold, V_(TO) is a threshold voltage of the first compensation transistor for zero substrate bias, γ is a body effect parameter, 2_(φF) is a surface potential, and V_(SB) is a difference between zero substrate bias and the value calculated to compensate for the offset.
 14. The sense amplifier circuit of claim 7, further comprising a built-in self-test (BIST) circuit configured to execute a test on the sense amplifier.
 15. A sense amplifier circuit comprising: a first power node having a first voltage value; a second power node having a second voltage value different from the first voltage value; a sense amplifier, the sense amplifier comprising: a first branch between the first power node and the second power node, the first branch comprising a first complementary transistor pair and a first input node between the transistors of the first complementary transistor pair; a second branch between the first power node and the second power node, the second branch comprising a second complementary transistor pair and a second input node between the transistors of the second complementary transistor pair; and a compensation transistor in the first branch or the second branch, wherein the first input node is coupled to a gate of each transistor of the second complementary transistor pair and the second input node is coupled to a gate of each transistor of the first complementary transistor pair; and an offset circuit configured to supply a compensation voltage to a bulk of the compensation transistor, the compensation voltage being selectable between the first voltage value and a compensation voltage value equal to the first voltage value increased or decreased by a re-offset voltage value.
 16. The sense amplifier circuit of claim 15, wherein the offset circuit comprises a pair of latched transistors, the first transistor of the pair of latched transistors is configured to pass the first voltage value to the bulk of the compensation transistor, and the second transistor of the pair of latched transistors is configured to pass the compensation voltage value to the bulk of the compensation transistor.
 17. The sense amplifier circuit of claim 16, wherein the offset circuit is configured to select between the first voltage value and the compensation voltage value in response to a pair of activation signals.
 18. The sense amplifier circuit of claim 16, wherein a gate of the compensation transistor is configured to receive the second voltage value.
 19. The sense amplifier circuit of claim 16, wherein the compensation transistor is a PMOS transistor and the second voltage value is ground.
 20. The sense amplifier circuit of claim 16, wherein the compensation transistor is an NMOS transistor and the first voltage value is ground. 